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SMBus/I 2 C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
Table 12. CLA0 (P2–P5) Configuration Register Setting (0x28) (continued)
FUNCTION
D5
D4
REGISTER BIT
D3 D2
D1
D0
2 input AND/OR P2 and P3 noninverted
0
0
2 input AND/OR P2 and P3 inverted
2 input AND/OR P2 inverted and P3
0
X
1
1
0
1
0
1
2 input AND/OR P2 and P3 both inverted
2 input AND/OR P2 and P4 noninverted
0
1
1
0
2 input AND/OR P2 and P4 inverted
2 input AND/OR P2 inverted and P4
1
1
0
0
X
1
0
1
2 input AND/OR P2 and P4 both inverted
2 input AND/OR P3 and P4 noninverted
1
0
0
1
2 input AND/OR P3 and P4 inverted
2 input AND/OR P3 inverted and P4
1
0
1
1
1
0
0
X
2 input AND/OR P3 and P4 both inverted
Table 13. Output P5 Configuration
1
1
BIT
D7
D6
LOGIC LEVEL
0
1
0
1
FUNCTION
Output not cascaded to CLA1
Output cascaded to CLA1
Output noninverted
Output inverted
Table 14. CLA1 (P6–P9) Configuration Register Setting (0x29)
FUNCTION
D5
D4
REGISTER BIT
D3 D2
D1
D0
XOR noninverted
0
0
XOR P7 inverted
XOR P6 inverted
0
1
X
1
0
X
0
1
XOR both ports inverted
1
1
3 input AND/OR all noninverted
3 input AND/OR P6 inverted
3 input AND/OR P7 inverted
0
0
0
0
0
1
0
1
0
3 input AND/OR P8 inverted
3 input AND/OR P6 and P7 inverted
1
0
1
1
1
0
1
1
0
3 input AND/OR P6 and P8 inverted
3 input AND/OR P7 and P8 inverted
3 input AND/OR all inverted
2 input AND/OR P6 and P7 noninverted
1
1
1
0
1
1
0
1
0
1
0
2 input AND/OR P6 and P7 inverted
2 input AND/OR P6 inverted and P7
0
X
1
1
0
1
0
1
2 input AND/OR P6 and P7 both inverted
1
1
18
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